Physical And Electrical Characteristics Of A High-k Yb_2o_3 Gate Dielectric

摘要

High-k ytterbium oxide (Yb_2O_3) gate dielectrics were deposited on Si substrate by reactive sputtering. The structural features of these films after postdeposition annealing treatment were studied by X-ray diffraction and X-ray photoelectron spectroscopy. It is found that the Yb_2O_3 gate dielectrics annealed at 700 ℃ exhibit a larger capacitance value, a lower frequency dispersion and a smaller hysteresis voltage in C-V curves compared with other annealing temperatures. They also show negligible charge trapping under high constant voltage stress. This phenomenon is mainly attributed to the decrease in the amorphous silica thickness.