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首页> 外文期刊>Applied Surface Science >Complete filling of 41 nm trench pattern using Cu seed layer deposited by SAM-modified electroless plating and electron-beam evaporation
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Complete filling of 41 nm trench pattern using Cu seed layer deposited by SAM-modified electroless plating and electron-beam evaporation

机译:使用通过SAM改性化学镀和电子束蒸发沉积的Cu种子层完全填充41 nm沟槽图案

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摘要

To overcome the limitation of the sputtered Cu seed layer in electroplating of Cu interconnects imposed by the shadow effect, a new method for depositing a Cu seed layer on a 41 nm trench pattern based on combination of electroless plating (ELP) and electron-beam (E-Beam) evaporation was developed. A Cu seed layer formed by ELP alone was too thin to be used for electroplating due to its high resistivity. To solve this problem, an additional Cu layer was deposited on top of the trench by E-Beam evaporator to enhance the electrical conductivity of the Cu seed layer. The electrical resistivity of the resulting Cu layer was reduced to 4.8 μΩ cm, which was sufficient for the conductive seed layer for electroplating the 41 nm trench pattern. The gap-filling capability also improved and there were no voids or seams in the 41 nm trench pattern. The proposed method can be an effective solution for fabrication of a conductive seed layer to fill a 41 nm trench pattern by electroplating.
机译:为克服阴影效应对电镀铜互连件造成的溅射铜籽晶层的局限性,一种基于化学镀(ELP)和电子束的结合在41 nm沟槽图案上沉积铜籽晶层的新方法(开发了电子束蒸发。仅由ELP形成的Cu籽晶层由于其高电阻率而太薄而不能用于电镀。为了解决该问题,通过电子束蒸发器在沟槽的顶部沉积了额外的铜层,以增强铜籽晶层的电导率。所得的Cu层的电阻率降低至4.8μΩcm,这对于用于电镀41nm沟槽图案的导电种子层是足够的。间隙填充能力也得到了改善,在41 nm沟槽图案中没有空隙或接缝。所提出的方法可以是用于制造导电种子层以通过电镀填充41nm沟槽图案的有效解决方案。

著录项

  • 来源
    《Applied Surface Science》 |2010年第8期|2649-2653|共5页
  • 作者单位

    Division of Materials Science and Engineering, Hanyang University, Seoul, 133-791, South Korea;

    Division of Materials Science and Engineering, Hanyang University, Seoul, 133-791, South Korea;

    Division of Materials Science and Engineering, Hanyang University, Seoul, 133-791, South Korea;

    Division of Materials Science and Engineering, Hanyang University, Seoul, 133-791, South Korea;

    Division of Materials Science and Engineering, Hanyang University, Seoul, 133-791, South Korea;

    R&D Divisions, Hynix Semiconductor Inc., San 136-1 Ami-ri Bubal-eub, Icheon-Si, Kyoungki-do, 467-701, South Korea;

    R&D Divisions, Hynix Semiconductor Inc., San 136-1 Ami-ri Bubal-eub, Icheon-Si, Kyoungki-do, 467-701, South Korea;

    R&D Divisions, Hynix Semiconductor Inc., San 136-1 Ami-ri Bubal-eub, Icheon-Si, Kyoungki-do, 467-701, South Korea;

    R&D Divisions, Hynix Semiconductor Inc., San 136-1 Ami-ri Bubal-eub, Icheon-Si, Kyoungki-do, 467-701, South Korea;

    Division of Materials Science and Engineering, Hanyang University, Seoul, 133-791, South Korea;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    electroplating; self-assembled monolayer; gap-filling capability; 41 nm trench pattern;

    机译:电镀;自组装单层;填补缺口的能力;41 nm沟槽图案;

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