Minimization of Parasitic Inductances in SFQ Circuits Using Over- and Under-Ground Planes

摘要

We designed the single-flux-quantum (SFQ) circuits that were fabricating using the NEC 2.5 ${hbox{kA/cm}}^{2}$ standard process that has four Nb layers. Before designing circuits with two ground planes, we estimated sheet inductances of the base and counter planes using simple rectangular-shape inductors. Estimated sheet inductance of the base plane was 0.75 of the original value for the circuits with only under-ground plane. For the counter plane, sheet inductance was estimated to be 0.55 of the original value. We designed a 2-branch D-FF gate and fabricated SFQ circuits including the 2-branch D-FF using the NEC standard process. Parasitic inductances of the counter layer in the 2-branch D-FF were effectively minimized using two ground planes and frequency dependences of the lower bias margin were improved.