Clock Line Considerations for an SFQ Large Scale Reconfigurable Data Paths Processor

摘要

We have estimated jitter accumulated in data and clock lines of an SFQ Reconfigurable Data Paths processor and its impact on the operating frequency and identified critical components. In order to prevent performance degradation, we have proposed to divide the processor in several parts clocked separately by an external jitter-free system clock. FIFO buffers and clock controllers inserted between the processor stages are used to synchronize each stage with the next one and as a result the accumulation of jitter is limited to one stage of the processor only. Two versions of a synchronization scheme prototype have been designed for both ISTEC-SRL standard 2.5 ${rm kA/cm}^{2}$ and advanced 10 ${rm kA/cm}^{2}$ processes and successfully tested at high speed.