Simulation of junctionless Si nanowire transistors with 3 nm gate length

摘要

Inspired by recent experimental realizations and theoretical simulations of thin siliconnnanowire-based devices, we perform proof-of-concept simulations of junctionless gated Si nanowirentransistors. Based on first-principles, our primary predictions are that Si-based transistors arenphysically possible without major changes in design philosophy at scales of u00041 nm wire diameternand u00043 nm gate length, and that the junctionless transistor avoids potentially serious difficultiesnaffecting junctioned channels at these length scales.We also present investigations into atomic-levelndesign factors such as dopant positioning and concentration. © 2010 American Institute of Physics.nu0005doi:10.1063/1.3478012