Conductance-voltage measurements on germanium nanocrystal memory structures and effect of gate electric field coupling

摘要

Conductance-voltage (G-V) analyses were performed on trilayer germanium (Ge) nanocrystal memory capacitor structures, consisting of a high dielectric constant (high-κ) layer (5 nm thick) grown on silicon, a sputtered Ge middle layer (4 nm thick), and a 20 nm thick sputtered cap oxide layer (either SiO_2 for moderate gate electric field coupling or HfAlO_x for better electric field coupling). Comparisons of the G-V characteristics were performed with a control capacitor sample without nanocrystals. The distinctive characteristics due to nanocrystals could be separated and identified from the interface traps provided the memory structure has sufficiently high electric field coupling from the gate applied voltage, resulting in a large electric field across the tunnel dielectric layer. This work attempts to provide an explanation to the G-V characteristics under the following three conditions: (1) interface trap dominated, (2) nanocrystal dominated, and (3) a combination of effects from both interface traps and nanocrystals. A method for estimating the density of nanocrystals based on the G-V data is also described.