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Planar junctionless transistor with non-uniform channel doping

机译:具有非均匀沟道掺杂的平面无结晶体管

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摘要

We propose a planar junctionless transistor (JLT) in silicon-on-insulator (SOI) with non-uniform channel doping in vertical direction to improve the ON to OFF drain current ratio. In single gate JLT in SOI, a thin device layer is depleted in the off-state from the top of the layer and the leakage current flows through bottom of the device layer, and the leakage current depends on the device layer thickness. We show that the decrease of doping in vertical direction suppresses the leakage current flowing through the bottom of the device by decreasing conductivity at the bottom of the device layer.
机译:我们提出了一种绝缘体上硅(SOI)中的平面无结晶体管(JLT),该沟道在垂直方向上掺杂了不均匀的沟道,以改善开/关漏极电流比。在SOI中的单栅JLT中,薄的器件层在截止状态从层的顶部耗尽,并且泄漏电流流过器件层的底部,并且泄漏电流取决于器件层的厚度。我们表明,垂直方向上掺杂的减少通过减小器件层底部的电导率来抑制流过器件底部的漏电流。

著录项

  • 来源
    《Applied Physics Letters》 |2013年第13期|133505.1-133505.3|共3页
  • 作者单位

    Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, India;

    Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, India,Microelectronics Research Center, 10100 Burnet Road, Bldg. 160, University of Texas at Austin, Austin, Texas 78758, USA;

    Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, India;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
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  • 入库时间 2022-08-18 03:16:25

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