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Formation of high-quality oxide/Ge_(1-x)Sn_x interface with high surface Sn content by controlling Sn migration

机译:通过控制Sn的迁移形成具有高表面Sn含量的高质量氧化物/ Ge_(1-x)Sn_x界面

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摘要

In this paper, we investigated how Sn migrated during annealing for Ge_(1-x)Sn_x at its surface and in its interior, as well as the Ge oxide formation on Ge_(1-x)Sn_x with controlling surface oxidation. After oxidation at 400 ℃, X-ray photoelectron spectroscopy and X-ray diffraction measurements revealed Sn migration from inside the epitaxial Ge_(1-x)Sn_x layer to its surface. Annealing was not the primary cause of significant Sn migration; rather, it was caused mostly by oxidation near the Ge_(1-x)Sn_x surface. This process formed a Ge_(1-x)Sn_x oxide with a very high Sn content of 30%, inducing a wide hysteresis loop in the capacitance-voltage characteristics of its corresponding MOS device. We also found that forming a thin GeO_2 layer by using a deposition method that controls Ge surface oxidation produced low densities of interface states and slow states. From these results, we conclude that controlling Sn migration is critical to forming a high-quality Ge_(1-x)Sn_x gate stack.
机译:在本文中,我们研究了退火过程中Sn对Ge_(1-x)Sn_x在其表面和内部的迁移过程,以及在控制表面氧化的情况下在Ge_(1-x)Sn_x上形成Ge氧化物的过程。在400℃下氧化后,X射线光电子能谱和X射线衍射测量表明Sn从外延Ge_(1-x)Sn_x层内部迁移到其表面。退火不是大量锡迁移的主要原因。相反,它主要是由Ge_(1-x)Sn_x表面附近的氧化引起的。该工艺形成了具有30%的极高Sn含量的Ge_(1-x)Sn_x氧化物,从而在其相应MOS器件的电容-电压特性中引起了宽的磁滞回线。我们还发现通过使用控制Ge表面氧化的沉积方法形成薄的GeO_2层会产生低密度的界面态和慢态。根据这些结果,我们得出结论,控制Sn的迁移对于形成高质量的Ge_(1-x)Sn_x栅堆叠至关重要。

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  • 来源
    《Applied Physics Letters》 |2014年第12期|122103.1-122103.5|共5页
  • 作者单位

    Department of Crystalline Materials Science, Graduate School of Engineering, Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8603, Japan, Department of Electrical Engineering and Computer Sciences, College of Engineering, University of California, Berkeley and Japan Society for the Promotion of Science (JSPS) Postdoctoral Fellow for Research Abroad;

    Department of Crystalline Materials Science, Graduate School of Engineering, Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8603, Japan, Innovations for High Performance (IHP) Microelectronics;

    Department of Crystalline Materials Science, Graduate School of Engineering, Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8603, Japan;

    Department of Crystalline Materials Science, Graduate School of Engineering, Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8603, Japan;

    Department of Crystalline Materials Science, Graduate School of Engineering, Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8603, Japan;

    Department of Crystalline Materials Science, Graduate School of Engineering, Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8603, Japan;

    Department of Crystalline Materials Science, Graduate School of Engineering, Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8603, Japan;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
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  • 入库时间 2022-08-18 03:16:01

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