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High gain, low noise, fully complementary logic inverter based on bi-layer WSe_2 field effect transistors

机译:基于双层WSe_2场效应晶体管的高增益,低噪声,完全互补逻辑反相器

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摘要

In this article, first, we show that by contact work function engineering, electrostatic doping and proper scaling of both the oxide thickness and the flake thickness, high performance p- and n-type WSe_2 field effect transistors (FETs) can be realized. We report record high drive current of 98 μA/μm for the electron conduction and 110 μA/μm for the hole conduction in Schottky barrier WSe_2 FETs. Then, we combine high performance WSe_2 PFET with WSe_2 NFET in double gated transistor geometry to demonstrate a fully complementary logic inverter. We also show that by adjusting the threshold voltages for the NFET and the PFET, the gain and the noise margin of the inverter can be significantly enhanced. The maximum gain of our chemical doping free WSe_2 inverter was found to be ~25 and the noise margin was close to its ideal value of ~2.5 V for a supply voltage of V_(DD) = 5.0 V.
机译:在本文中,首先,我们展示了通过接触功函数工程,静电掺杂以及氧化物厚度和薄片厚度的适当缩放,可以实现高性能的p型和n型WSe_2场效应晶体管(FET)。我们报道在肖特基势垒WSe_2 FET中,电子传导的驱动电流高达98μA/μm,空穴传导的驱动电流高达110μA/μm。然后,我们将高性能WSe_2 PFET与WSe_2 NFET结合在双栅极晶体管的几何结构中,以演示完全互补的逻辑反相器。我们还表明,通过调整NFET和PFET的阈值电压,可以显着提高反相器的增益和噪声容限。我们发现无化学掺杂的WSe_2逆变器的最大增益为〜25,并且在电源电压V_(DD)= 5.0 V时,噪声容限接近其理想值〜2.5V。

著录项

  • 来源
    《Applied Physics Letters》 |2014年第8期|083511.1-083511.5|共5页
  • 作者单位

    Center for Nanoscale Material, Argonne National Laboratory, Argonne, Illinois 60439, USA;

    U.S. Army Research Laboratory, Adelphi, Maryland 20783, USA;

    Center for Nanoscale Material, Argonne National Laboratory, Argonne, Illinois 60439, USA;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
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