An area-power efficient 4-PAM full-clock 10-Gb/s CMOS pre-emphasis serial link transmitter

摘要

This paper presents a new area-power efficient 4-PAM full-clock CMOS pre-emphasis transmitter for 10-Gb/s serial links. The proposed transmitter reduces the chip area and power consumption by minimizing the number of digital-to-analog converters for 4-PAM signaling and pre-emphasis. In addition, a new full-clock scheme is proposed to double the data rate without increasing the sampling clock frequency. To assess the effectiveness of the proposed transmitter, a 8-to-1 serial link consisting of the proposed transmitter and a pair of terminated microstrip lines with a FR4 substrate has been implemented in TSMC 0.18 μm 1.8 V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3.3V transistor models that count for both device parasitics and second-order effects. Simulation results are presented.