首页> 外文期刊>Analog Integrated Circuits and Signal Processing >An area-power efficient 4-PAM full-clock 10-Gb/s CMOS pre-emphasis serial link transmitter
【24h】

An area-power efficient 4-PAM full-clock 10-Gb/s CMOS pre-emphasis serial link transmitter

机译:区域电源高效的4-PAM全时钟10 Gb / s CMOS预加重串行链路发送器

获取原文
获取原文并翻译 | 示例

摘要

This paper presents a new area-power efficient 4-PAM full-clock CMOS pre-emphasis transmitter for 10-Gb/s serial links. The proposed transmitter reduces the chip area and power consumption by minimizing the number of digital-to-analog converters for 4-PAM signaling and pre-emphasis. In addition, a new full-clock scheme is proposed to double the data rate without increasing the sampling clock frequency. To assess the effectiveness of the proposed transmitter, a 8-to-1 serial link consisting of the proposed transmitter and a pair of terminated microstrip lines with a FR4 substrate has been implemented in TSMC 0.18 μm 1.8 V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3.3V transistor models that count for both device parasitics and second-order effects. Simulation results are presented.
机译:本文提出了一种用于10 Gb / s串行链路的新型区域功率高效的4-PAM全时钟CMOS预加重发送器。所提出的发送器通过最小化用于4-PAM信令和预加重的数模转换器的数量,减少了芯片面积和功耗。另外,提出了一种新的全时钟方案,以在不增加采样时钟频率的情况下使数据速率加倍。为了评估建议的发射器的有效性,已在TSMC 0.18μm1.8 V CMOS技术中实现了由建议的发射器和一对带有FR4基板的端接微带线组成的8对1串行链路,并使用了Cadence的SpectreRF进行了分析具有BSIM3.3V晶体管模型的设计系统可同时考虑器件寄生效应和二阶效应。给出了仿真结果。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号