A low-voltage low-power programmable fractional PLL in 0.18-μm CMOS process

摘要

The prolific growth of portable electronic devices (PED) has generated tremendous interests among researchers to develop programmable phase-locked loops (PLLs) because of their abilities to produce multiple spectrally pure output frequencies from a fixed frequency oscillator. The power consumption of the RF block of a PED is mostly dominated by the programmable PLLs which are widely used in the design of these devices. Therefore to reduce the overall power consumption in a portable device and to increase the battery life time, low-voltage and low-power are the two key requirements for the PLL design. In this work an improved programmable fractional frequency divider has been incorporated to enhance the overall performance of the PLL that includes lower operating supply voltage and lower power consumption compared to the state-of-art. The proposed programmable fractional PLL has an operating frequency in the range of 1.7–2.5 GHz, and a frequency resolution of 2.5 MHz. Measurement results reveal that the proposed programmable PLL can operate at 2.4 GHz with a 1.46 V power supply voltage and only 10 mW of power consumption.