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Widely tunable low-power high-linearity current-mode integrator built using DG-MOSFETs

机译:利用DG-MOSFET构建的可调谐低功耗高线性度电流模式积分器

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A novel tunable current-mode integrator for low-voltage low-power applications is presented using mixed-mode TCAD simulations. The design is based on independently driven double-gate (IDDG) MOSFETs, a nano-scale four-terminal device, where one gate can be used to change the characteristics of the other. Using current-mirrors built with IDDG-MOSFETs, we show that the number of active devices in the tunable current-mode integrator, 16 in bulk CMOS design, may be halved, i.e. considerable savings in both total area and power dissipation. The integrator operates with single supply voltage of 1 V and a wide range of tunable bandwidth (~2 decades) and gain (~30 dB). This linear circuit has third-order harmonic distortion as low as −70 dB in appropriate bias conditions, which can be set via the back-gates. The impact of tuning on the IDDG integrator and conventional design using symmetrically driven (SDDG) MOSFETs is comparatively studied. The proposed design is a good example for performance leverage through IDDG MOSFET architectures in analog circuits integral to future mixed-signal systems. Keywords CMOS analog integrated circuits - Integrators - DG-MOSFET - SOI
机译:利用混合模式TCAD仿真,提出了一种适用于低压低功率应用的新型可调电流模式积分器。该设计基于独立驱动的双栅极(IDDG)MOSFET,这是一种纳米级的四端子器件,其中一个栅极可用于改变另一个栅极的特性。使用IDDG-MOSFET内置的电流镜,我们显示出可调谐电流模式积分器中的有源器件数量(在批量CMOS设计中为16个)可以减半,即在总面积和功耗上都可节省很多。积分器以1 V的单电源电压和宽范围的可调带宽(〜2十倍)和增益(〜30 dB)工作。在适当的偏置条件下,该线性电路具有低至-70 dB的三阶谐波失真,可以通过后栅极进行设置。比较研究了调谐对IDDG积分器和使用对称驱动(SDDG)MOSFET的常规设计的影响。拟议的设计是通过IDDG MOSFET架构在未来混合信号系统必不可少的模拟电路中提高性能的一个很好的例子。 CMOS模拟集成电路-积分器-DG-MOSFET-SOI

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