Testability Design for Sleep Convention Logic

摘要

Memories of Flash are one more type of memory of non-volatile type on floating-gate transistors. The advantage of commodity and embedded flash memories will have rapid growth while we enter in the era of system-on-chip. Conventional tests for flash memory are usually ad hoc is the test procedure which is developed for a specific design. As there is a very large number of possible failure modes for flash memories. algorithms of long test that is automatic test equipment (ATE) which is complicated are usually seen. Production column and row address bit cell as basis to probe for any possible weaknesses of the process or design in SRAM. There occur faults saO and sal in any chip design, these faults will be overcome by using row, column address cells we make very perfect location to store the data or matter and cross sections of SRAMS will not occur. By the extend of cell check for memory array will verify the memory location for fault detection. The row address buffer and column address buffer will be used to pick the memory location. By comparing with previous method the above two modules gives accurate selection result for memory location for operation of cell checking.