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首页> 外文期刊>ACM transactions on reconfigurable technology and systems >In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms
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In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms

机译:现代异构CPU-FPGA平台的微体系结构的深入分析

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摘要

Conventional homogeneous multicore processors are not able to provide the continued performance and energy improvement that we have expected from past endeavors. Heterogeneous architectures that feature specialized hardware accelerators are widely considered a promising paradigm for resolving this issue. Among different heterogeneous devices, FPGAs that can be reconfigured to accelerate a broad class of applications with orders-of-magnitude performance/watt gains, are attracting increased attention from both academia and industry. As a consequence, a variety of CPU-FPGA acceleration platforms with diversified microarchitectural features have been supplied by industry vendors. Such diversity, however, poses a serious challenge to application developers in selecting the appropriate platform for a specific application or application domain.This article aims to address this challenge by determining which microarchitectural characteristics affect performance, and in what ways. Specifically, we conduct a quantitative comparison and an in-depth analysis on five state-of-the-art CPU-FPGA acceleration platforms: (1) the Alpha Data board and (2) the Amazon F1 instance that represent the traditional PCIe-based platform with private device memory; (3) the IBM CAPI that represents the PCIe-based system with coherent shared memory; (4) the first generation of the Intel Xeon+FPGA Accelerator Platform that represents the QPI-based system with coherent shared memory; and (5) the second generation of the Intel Xeon+FPGA Accelerator Platform that represents a hybrid PCIe-based (non-coherent) and QPI-based (coherent) system with shared memory. Based on the analysis of their CPU-FPGA communication latency and bandwidth characteristics, we provide a series of insights for both application developers and platform designers. Furthermore, we conduct two case studies to demonstrate how these insights can be leveraged to optimize accelerator designs. The microbenchmarks used for evaluation have been released for public use.
机译:传统的同质多核处理器无法提供我们过去所做的努力所期望的持续性能和能源改进。具有专用硬件加速器的异构体系结构被广泛认为是解决此问题的有希望的范例。在不同的异构器件之间,可以重新配置以加速数量级性能/功率增益的各种应用的FPGA引起了学术界和工业界的越来越多的关注。结果,行业供应商已经提供了具有多样化微体系结构功能的各种CPU-FPGA加速平台。但是,这种多样性给应用程序开发人员在为特定应用程序或应用程序领域选择合适的平台时提出了严峻的挑战。本文旨在通过确定哪些微体系结构特征以及以何种方式影响性能来应对这一挑战。具体来说,我们对五个最新的CPU-FPGA加速平台进行了定量比较和深入分析:(1)Alpha数据板和(2)代表传统基于PCIe的Amazon F1实例具有专用设备内存的平台; (3)IBM CAPI,它表示具有一致共享内存的基于PCIe的系统; (4)第一代Intel Xeon + FPGA加速器平台,代表具有连贯共享内存的基于QPI的系统; (5)第二代英特尔®至强®FPGA加速器平台,该平台代表了具有共享内存的基于PCIe的(非一致性)和基于QPI的(一致性)混合系统。基于对他们的CPU-FPGA通信延迟和带宽特性的分析,我们为应用程序开发人员和平台设计人员提供了一系列见解。此外,我们进行了两个案例研究,以展示如何利用这些见解来优化加速器设计。用于评估的微基准已经发布供公众使用。

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    Univ Calif Los Angeles, Ctr Domain Specif Comp, Engn 6,404 Westwood Plaza, Los Angeles, CA 90095 USA;

    Univ Calif Los Angeles, Ctr Domain Specif Comp, Engn 6,404 Westwood Plaza, Los Angeles, CA 90095 USA;

    Univ Calif Los Angeles, Ctr Domain Specif Comp, Engn 6,404 Westwood Plaza, Los Angeles, CA 90095 USA;

    Univ Calif Los Angeles, Ctr Domain Specif Comp, Engn 6,404 Westwood Plaza, Los Angeles, CA 90095 USA;

    Univ Calif Los Angeles, Ctr Domain Specif Comp, Engn 6,404 Westwood Plaza, Los Angeles, CA 90095 USA;

    Univ Calif Los Angeles, Ctr Domain Specif Comp, Engn 6,404 Westwood Plaza, Los Angeles, CA 90095 USA;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Heterogeneous computing; CPU-FPGA platform; Xeon plus FPGA; CAPI; AWS F1;

    机译:异构计算;CPU-FPGA平台;Xeon plus FPGA;CAPI;AWS F1;

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