基于FPGA的高速高阶FIR数字滤波器的设计

摘要

在数字滤波器设计与应用当中，相比于以牺牲线性相位频率特性为代价的无限冲击响应（IIR）数字滤波器，有限冲击响应（FIR）数字滤波器不仅保证了精确严格的线性相位特性，并且结构简单稳定。但在实现相同的设计指标时，有限冲击响应需要更高的阶数，为满足高速高阶数字滤波器设计，文章提出一种改进的分布式算法。该算法利用主流现场可编程逻辑门阵列（FPGA）芯片的多相分解结构和流水线技术，采用多路复用加法器对数据进行预相加，减少传统分布式结构的查找表规模。利用Matalb仿真设计，Quartus II编译测试，并下载到现场可编程门阵列（FPGA）中进行运行分析，结果显示文章的方法有效地减少了滤波器对硬件资源的消耗，能够较好地实现高阶的FIR滤波器。%Compared with the expense of the linear phase frequency characteristic of Infinite Impulse Response (IIR) digital filter, Finite Impulse Response (FIR) digital iflter not only ensures the accurate strict linear phase characteristic, simple structure and stable in the design and application of digital iflter. But the FIR need higher order when complete the same design index, this paper proposes an improved distributed algorithm in order to meet the design of high-speed and high-order digital FIR iflter. The algorithm uses the Polyphase decomposition and pipeline technology and multiplexing adder pre-add the data to reduce the Look up Table (LUT) size of the traditional distribute algorithm of mainstream Field Programmable Gate Array (FPGA) chip . The paper makes use of Matlab simulation design, Quartus II compile testing and downloads to the Field Programmable Gate Array(FPGA) to analysis, the results show that the method effectively reduces the iflter to the consumption of hardware resources, can realize the high-order FIR iflter in a more appropriate way.