LDPC码快速编码器的DSP设计与实现

摘要

对CCSDS131.1-0-2(Experimental Specification)中提出的一类准循环LDPC删余码进行研究,分析了该类码的特点,并仿真了其性能;结合其特点,对编码中的"贪婪算法"进行一定的改进,设计了快速编码算法.通过对TMS320C6416DSP平台的功能与运算技巧的结合,对编码算法代码进行合理优化,完成了快速编码器的DSP实现,编码速率达到30Mbit/s.%The punctured Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) code proposed by CCSDS 131.1-O-2 (Experimental Specification) is investigated. First, the characteristics of the codes are analyzed, and its decoding performance is simulated. Then, the encoding method called “Greedy Algorithm" combining with the code's character is improved, and a fast encoding method is proposed. At last, how to optimize the encoding method by taking good use of the functions afforded by the DSP TMS320C6416 platform and skills of operations is described. The encoding rate can achieve 30 Mbit/s based on DSP.