FPGA/CPLD在数字系统开发的应用日益广泛，影响到生产生活的方方面面。电子计数式频率计在各种电子测量领域应用广泛。为了降低频率计的量化误差，提高频率测量精度，在Quartus Ⅱ9.0开发环境下，用VHDL语言设计了一种能在1 Hz~100 MHz频率范围内使频率测量相对量化误差小于10-5的高精度数字频率计，仿真结果表明，所设计的数字频率计达到了设计精度要求，并能准确显示测量数值。最后，以Cyclone Ⅱ系列EP2C20F484C7芯片为硬件环境，验证了各项设计功能的正确性。%The application of the FPGA/CPLD becomes more and more extensive in the design of digital systems and it has affected people’s life deeply,so the electronic counter type frequency meter is widely used in various electronic measurement fields. In order to reduce quantization error of the frequency meter and improve the accuracy of frequency measurement,a high-precision digital frequency meter whose relative quantization error is less than 10-5 was designed with VHDL language under the development environment of Quartus Ⅱ9.0. Its frequency measurement range is 1 Hz~100 MHz. The simulation results indicate that the digital frequency meter can meet accuracy requirements,and can accurately display measured value. The correctness of all the designed functions was validated with the EP2C20F484C7 chip of Cyclone Ⅱ series.
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