脉冲信号数字滤波以及无缝计数电路设计

摘要

There are random interfering signals in the output pulse signal of inertial navigation components. In order to reduce the impact of interfering signals on the performance of inertial navigation component, a FPGA-based pulse signal digital filter is designed, and a seamless count is implemented for the filtered pulse signal once evey 5 ms. The count results is sent to host computer by serial bus to display and process. After a long period of system testing, output pulse signal frequency of inertial navigation components reaches up to 13 MHz by the method. It filteres interference signal in the range of 50 kHz~12. 5 MHz, which meets the test requirements.%惯导产品输出脉冲信号存在干扰信号,为减少其对惯导产品性能的影响,文中设计了一种基于FPGA的脉冲信号数字滤波器,并对滤波后脉冲信号以5 ms为计数单元进行无缝计数,计数结果可由串行总线上传至上位机进行显示和处理.通过该方法测量的惯导产品输出脉冲信号频率最高可达13 MHz,其中可对频率范围为50 kHz～12.5 MHz的干扰信号进行滤除,满足惯导产品性能测试要求.