时间交叉存取逐次逼近型ADC中的电容自校准技术

摘要

A capacitor self-calibration circuit used in a successive approximation analog-to-digital converter(SA-ADC) is presented. This capacitor self-calibration circuit can calibrate erroneous data and work with the ADC by adding an additional clock period. This circuit is used in a 10 bit 32 Msample/s time-interleaved SAADC. The chip is implemented with Chart 0. 25 μm 2. 5 V process and totally occupies an area of 1.4 mm × 1.3mm. After calibration, the simulated signal-to-noise ratio (SNR) is 59. 586 1 dB and the spurious-free dynamic range (SFDR) is 70. 246 dB at 32 MHz. The measured signal-to-noise and distortion ratio (SINAD) is 44. 82 dB and the SFDR is 63. 760 4 dB when the ADC samples a 5.8 MHz sinusoid wave.%设计了一种用于逐次逼近型ADC中的电容自校准电路.通过增加一个校准周期,该电容自校准结构即可与原电路并行工作,并可校准电路工作时产生的误差.采用该电路设计了一个用于多通道逐次逼近型结构的10 bit 32 Msample/s模数转换器单元,该芯片在Chart 0.25 μm 2.5 V工艺上实现,总的芯片面积为1.4 mm×1.3 mm.在32 MHz工作时,通过校准后的信噪比仿真结果为59.586 1 dB,无杂散动态范围为70.246 dB.芯片实测,输入频率5.8 MHz时,信噪失真比为44.82dB,无杂散动态范围为63.760 4 dB.