首页> 外文期刊>东南大学学报(英文版) >433 MHz低功耗CMOS LNA的噪声优化与实现
【24h】

433 MHz低功耗CMOS LNA的噪声优化与实现

机译:433 MHz低功耗CMOS LNA的噪声优化与实现

获取原文
获取原文并翻译 | 示例
       

摘要

采用0.18μm SMIC数模混合与射频(RF)CMOS工艺实现了一个应用于ISM(工业、科学和医疗)频段接收机的433 MHz低功耗低噪声放大器(LNA)的设计.电路通过调节源级反馈电感和在LNA输入晶体管上并联电容的方法实现了最优的噪声性能.测试结果表明,LNA在431 MHz处的噪声系数为2.4 dB,S21=16 dB,S11=-11 dB,S22=-9 dB,反向隔离度大于35 dB.测量的1-dB压缩点(P1dB)和输入三阶交调(ⅡP3)分别为-13dBm和-3 dBm.芯片面积为0.55 mm×1.2 mm,在1.8 V供电时整个电路功耗仅4 mW.%A loW power 433 MHz CMOS(complementary metal-oxide-semiconductor transistor)loW noise amplifier(LNAl),used for an ISM (industrial-scientific-medical)receiver, is implemented in a 0.18 μm SMIC mixed-signal and RF(radio frequency)CMOS process.The optimal noise perfommce of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA.The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB.The S21 is equal to 16 dB,S11=-11 dB,S22=-9 dB,and the inverse isolation is 35 dB.The measured input 1-dB compression point (P1dB)and input third-order mtermodulation product(ⅢP3)are -13 dBm and-3 dBm,respectively.The chip area is 0.55 mm ×1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.
机译:采用0.18μm SMIC数模混合与射频(RF)CMOS工艺实现了一个应用于ISM(工业、科学和医疗)频段接收机的433 MHz低功耗低噪声放大器(LNA)的设计.电路通过调节源级反馈电感和在LNA输入晶体管上并联电容的方法实现了最优的噪声性能.测试结果表明,LNA在431 MHz处的噪声系数为2.4 dB,S21=16 dB,S11=-11 dB,S22=-9 dB,反向隔离度大于35 dB.测量的1-dB压缩点(P1dB)和输入三阶交调(ⅡP3)分别为-13dBm和-3 dBm.芯片面积为0.55 mm×1.2 mm,在1.8 V供电时整个电路功耗仅4 mW.%A loW power 433 MHz CMOS(complementary metal-oxide-semiconductor transistor)loW noise amplifier(LNAl),used for an ISM (industrial-scientific-medical)receiver, is implemented in a 0.18 μm SMIC mixed-signal and RF(radio frequency)CMOS process.The optimal noise perfommce of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA.The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB.The S21 is equal to 16 dB,S11=-11 dB,S22=-9 dB,and the inverse isolation is 35 dB.The measured input 1-dB compression point (P1dB)and input third-order mtermodulation product(ⅢP3)are -13 dBm and-3 dBm,respectively.The chip area is 0.55 mm ×1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号