小数分频频率合成器中Σ-Δ调制器设计与实现

摘要

介绍了一种应用于小数分频频率合成器的Σ-Δ调制器的设计,该调制器采用三阶级联的MASH1-1-1结构,并利用流水线技术,提高了调制器的工作频率.电路设计采用Verilog HDL硬件描述语言实现,基于 QuartusⅡ工具进行测试验证,结果表明,调制器最高工作频率为240.56 MHz.最终采用 SMIC 0.18μm CMOS 工艺,完成了电路版图设计.芯片面积为34148.5μm2,芯片总功耗为1.284 mW,与传统设计相比,面积降低了31.23%,功耗降低了46.14%.%This paper presented a design and implementation study of a three-order all-digital MASHΣ-Δmodulator,which can be used in Fractional-N Frequency Synthesizer applications.To achieve the de-sired operation frequency while providing low-power dissipation and small area,the pipelining technique was utilized in the design.The circuit was described by using the Verilog hardware description language, and the operating frequency of the modulator is 240.56 MHz based on QuartusⅡ.Eventually,the SMIC 0.18μm CMOS process was adopted,and the circuit layout was completed.The chip's area is 34148.5μm2 ,and the total power of the chip is 1.28 mW.Compared with traditional design,it can result in a 31. 23% area reduction and 46.14% power reduction.