一种混合相容数据块的测试数据压缩方案

摘要

针对SOC芯片测试数据快速增长的特点,提出了一种有效的测试数据压缩方案.该方案根据测试数据中存在大量无关位,测试数据存在相容性的特点,采用二进制代码来表示具有相容性的测试数据,对符合条件的测试数据采用一位压缩,提高了编码压缩效率.同时提出了一种基于有限状态机和循环移位寄存器的解压缩算法的实现方案,对ISCAS 89部分标准电路实验结果表明,该方案跟同类方案相比,最高平均差值压缩率为13.32％,具有高压缩率、硬件实现简单等特点.%According to the characteristics of test data of the SOC rapid increasing, a test data compression scheme based on mixed compatible date blocks is presented. In the scheme, binary code is used to express the test data which are compatible with reference data, and eligible test data are compressed with one-bite compression, which are improved compression radio. The circuit structure of decoder with a finite state machine ( FSM) and a cyclical scan register ( CSR) was proposed. Experimental results show that this scheme is a more efficient compression method than other compression schemes and the highest average difference compression rate is 13. 32%.