基于FPGA的改进DES加密算法的实现

摘要

本文针对基于FPGA硬件设计方法的特点,对DES( data encryption standard)加密算法进行了深入分析,提出了一种基于现场可编程阵列(FPGA)的DES改进算法.该算法采用3级流水线生成子密钥,提高了子密钥的生成速度；采用状态机方法控制子密钥的产生时间,避免出现时钟延时；而且S盒随时间的变化可动态刷新,从而实现牢不可破的“一次一密”的密码体制.最后给出了由VHDL描述语言实现的硬件算法,并在Xilinx Virtex- Ⅱ Pro平台上进行了仿真实验,结果表明了硬件实现算法的正确性,而且系统硬件资源消耗有所降低,系统的处理速度得到较大提高.因此基于FPGA实现的DES加密算法适用于实时性较强的场合.%This paper analyzes DES (data encryption standard ) algorithm deeply, according to the characteristics of hardware design methods based on FPGA, an improved DES algorithm is adapted. The algorithm uses three lines to generate sub-keys and increase the speed of sub-key generation significantly. Also it utilizes the state machine approach to control the window time of sub-key generation in order to avoid clock delay, and S-box can be dynamically refreshed and come to the situation which is too strong to achieve the "one time padding" cipher system. Finally, the algorithm on FPGA is realized through hardware description language, and Xilinx Virtex-II Pro platform for the simulation results show that the algorithm implemented in hardware is correct, and hardware resource consumption is reduced. In addition, the processing speed of system is greatly enhanced. So DES encryption algorithm based on FPGA is fit for real-time strong scenarios.