利用基本 RS 锁存器设计仲裁逻辑电路方法

摘要

The exclusive characteristics of output state often ignored in basic RS latch circuit can be made full use of. When the circuit's input signal goes against constraints and then back to satisfy them,internal circuit only exists one winning output state through automatical competition. The arbitration logic circuit is designed according to basic RS latch circuit's principle. Then,it's corresponding working principle of storage and recovery circuit is expounded in detail. By simulation,the correctness of the design is verified.%基本 RS 锁存器电路有一个常被忽视但可以充分利用的输出状态排它性特点：当基本 RS 锁存器电路输入信号状态先违背约束条件再符合约束条件时，内部电路自动竞争后只能有一个输出状态胜出。笔者借鉴基本 RS 锁存器电路工作原理设计出仲裁逻辑电路，之后对仲裁逻辑电路以及与之配套的存贮和复原电路工作原理进行了详细阐述，并通过仿真验证了仲裁逻辑电路设计的正确性。