为了实现可逆逻辑电路的可测性设计,充分利用可逆逻辑电路中存在的输出引脚,提出一种可逆逻辑电路测试综合方法.通过定义可逆逻辑门的可观性值和可控性值的计算方法,对可逆逻辑电路的可测性进行建模；通过插入观察点,制定了可逆组合逻辑电路可测性实现方案；通过对现有的D触发器进行改造并构建全新的扫描D触发器,制定了可逆时序电路的可测性逻辑实现方案；最后分析了扫描D触发器的工作特点,规范了测试步骤,建立一种可逆逻辑电路的测试综合方法.实验结果表明,与现有方法相比,文中方法插入观察点代价平均增加不到1％,但电路的可观性平均能得到24％的改善.%A test-synthesis method of reversible circuits is proposed. Firstly, definition of measuring controllability and observability for reversible logic is given. Secondly, a new plan of Design-For-Test for reversible combinational and sequential circuits is worked out. Thirdly, a D Flip-Flops for reducing cost is built and a new scan-D Flip-Flops for constructing scan-chains is provided. Finally, utilizing the new scan-D Flip-Flops, a Test-Synthesis method for reversible circuits was presented. The proposed method was tested on a set of reversible benchmarks. In comparison with existing methods, costs increased less than 1 percent, while the improvement of testability has reached by 24 percent.
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