A pretreatment systolic array hardware architecture is proposed based on full-search algorithm of motion estimation. This architecture reduces 12. 3％ compared with non-power processing primitive systolic array. Based on this, futher manages circuit according to the logic producing gating clock as well as stopping register chain, and achieves 69.2％ power savings.%基于运动估计的全搜索算法,人们提出了有预处理的脉动阵列硬件结构,相较于无功耗处理的原始脉动阵列减少了12.3%.在此基础上,进一步根据逻辑产生门控时钟以及停止寄存器链对电路进行管理,取得了69.2%的功耗节省.
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