二维OS-CFAR检测器在雷达目标检测中具有较好的检测性能,特别是在多目标以及动态杂波环境中 ,具有较强的抗干扰目标的能力.本文基于FPGA 设计和实现了二维OS-CFAR检测器 ,采用并行寻址以及二元积累判决等结构解决了FPGA 实现中二维空间上参考单元寻址困难以及排序运算计算量大、耗时长、实时性不高的问题 ,实现了对距离-多普勒平面内所有检测点的流水作业 ,提高了二维有序恒虚警检测的实时性 ,满足了工程应用的要求.通过将FPGA实现结果与理论检测结果进行比较 ,验证了本文方法的有效性.%Two-dimensional (2D ) Ordered Statistics Constant False Alarm Rate (OS-CFAR) detector usually exhibits good performance in radar target detection .It has good an-ti-jamming capacity especially in the non-homogeneous environment caused by strong inter-fering targets and dynamic clutter .In this paper ,a 2D OS-CFAR detector is designed and implemented based on FPGA .The structures ,including parallel addressing and binary inte-gration decision ,are exploited to resolve the problems such as difficulty in reference cell ad-dressing ,large computation amount ,time consuming and low real-time poverty in the orde-ring process ,which often occur in the implementation process with FPGA .All the points in the Range-Doppler plane are detected in data flow processing and the real-time poverty of the 2D OS-CFAR is improved ,which meets the requirements in engineering .A comparison of the experimental results based on FPGA and the theoretical analysis is conducted and demon-strates the effectiveness of the proposed method .
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