定时同步信号产生电路的设计与实现

摘要

定时器是信号接收机系统的重要组成部分,它为整个系统提供所需的各种主脉冲定时信号和波门定时信号.传统的定时器大多采用纯硬件的实现方法,利用分立元件搭建逻辑电路,造成了其电路复杂、工作量大、可读性差、可靠性低的不良表现.提出一种基于FPGA的定时器,采用STM32F407为微处理器输出频率控制信号,为信号接收机系统提供了定时信号输入和频率控制信号;最后,利用Verilog HDL和相关程序语言对FPGA和相关模块进行软件编程设计.%The timer is an important part of the signal receiver system,which provides a variety of main pulse timing signals and gate timing signals for the entire system. Most of the traditional timers use the method of pure hardware,it utilizes the discrete components to build logic circuit,which resulting in the poor performance such as complex circuit,heavy workload,poor readability and low reliability. In this paper,an FPGA- based timer proposed uses the STM32F407 to output the frequency control signal for the microprocessor,which provides the timing signal input and frequency control signal for the signal receiver system;finally,the use of Verilog HDL and related programming language FPGA and related modules for software programming.