Settling Time of Mesochronous Clock Retiming Circuits in the Presence of Timing Jitter

摘要

It is well known that timing jitter can degrade the bit error rate (BER) ofreceivers that recover clock information from the input data. However, timingjitter can also result in an indefinite increase in the settling time of clockrecovery circuits at the receivers, particularly in low swing mesochronoussystems. Mesochronous clock retiming circuits are required in repeaterless lowswing on-chip interconnects in order to sample the low swing data at the centerof the eye. This paper discusses the settling time of these circuits. First, adiscussion on how timing jitter can result in large increase in the settlingtime of the clock recovery circuit is presented. Next, the circuit is modeledas a Markov chain with absorbing states. Here, the mean time of absorption ofthe Markov chain, which represents the mean settling time of the circuit, isdetermined. The model is validated by using behavioural simulations of thecircuit, the results of which match well with the model predictions. Themodelling is applied to study the effect of different types of jitter, likedata dependent jitter of 1 bit and 2 bits, random jitter and random jitteralong with 1 bit data dependent jitter. Finally, a few techniques of reducingthe settling time are presented and their efficacy is confirmed with circuitsimulations.