基于CPLD的LVDS数据传输系统的设计与研究

摘要

In order to solve the high-speed signal processing and transmission bottlenecks in data transfer speed distance problems, a CPLD-based high-speed LVDS bus data transfer system is designed, constructed a kind of LVDS chips, drives and high-speed adaptive equalizer for the based transmission system, the introduction of chip FIFO （FIFO） as a data buffer, the system using XILINX CPLD real-time control and monitoring, and fully taking into account that there is no synchronization of data transmission should take effective measures. Internal control procedures designed and implemented using VHDL language, reducing system complexity and cost, improved system integration and stability. Modelsim software application designed system was timing simulation, the simulation results obtained verify the design requirements.%为解决目前高速信号处理中的数据传输速度瓶颈以及传输距离的问题,设计并实现了一种基于CPLD的LVDS总线高速数据传输系统,构建了一种以LVDS芯片、高速驱动器,以及自适应均衡器为基础的传输系统,引入先进先出芯片（FIFO）作为数据缓冲,利用XILINX CPLD对系统进行实时控制与监测,并且充分考虑到数据传输过程出现不同步时应该采取的有效措施。内部控制程序利用VHDL语言设计实现,降低了系统的复杂度和成本,提高了系统集成度和稳定性。应用Modelsim软件对设计系统进行了时序仿真,得出的仿真结果验证其达到了设计要求。