全并行FIR滤波器的FPGA实现与优化

摘要

FIR digital filter has many implementations, and the needs of real-time modern digital communication require high data throughput and processing speed. The paper introduces the FPGA implementation of high-speed and fully parallel FIR, then takes 8-input and 15-tap FIR filter for example, getting fully parallel FIR structure based on the direct FIR .The fully parallel FIR structure is designed with Verilog hardware description language, and the result of simulation and test is consistent with MATLAB. On that basis, we raise two measures for improvement, then synthesis, placement and routing, and compare the occupied resource. The result is that the distributed FIR is the best choice of hardware implementation.%FIR数字滤波器的实现方法很多,而现代数字通信对实时性的需求决定其需要很高的数据吞吐率和处理速度.文章探求高速全并行FIR的FPGA实现方法,并以8输入15阶FIR滤波器为示例,在直接型FIR的基础上改进得到全并行FIR结构,采用Verilog硬件描述语言完成设计,仿真结果与MATLAB软件测试结果一致. 在此基础上,提出两种改进措施,并进行综合、布局布线,对比所占资源,结果分布式FIR为硬件实现的最佳选择.