A 12bit 8GSps current-steering digital-to-analog converter (DAC) based on a 0.7μm InP HBT process was designed. A double-sampling technology was adopted to increase the sampling rate to twice the clock frequency. Besides, the double-samplingswitch and current switch were separated to decrease the inter-symbol-interference. A "keep on current" method was used for reference to improve the architecture of current switch. The new architecture enlarged output impedance, suppressed harmonic distortion and optimized the dynamic performance. Simulation results show that the chip consumes a power of 2.45 W and achieves a DNL and INL of 0.4 and 0.35 LSB, respectively. The spurious-free-dynamic-range(SFDR) at low frequency is above 71.53 dBc and the lowest SFDR up to Nyquist frequency is 50.54 dBc. The SFDR performance is above 50 dBc over the whole 1st Nyquist region and it meets the system requirements of high-end test instruments.%设计了一种基于0.7μm的InP HBT工艺设计的12位8GSps的电流舵型数模转换器(DAC).采用双采样技术,将输出采样率提高为时钟频率的两倍.并且将双采样开关与电流开关分离以减小码间串扰.借鉴常开电流源法改进了电流源开关结构.新的结构增大了输出阻抗和稳定性,抑制了谐波失真,提高了芯片动态性能.通过仿真结果得到,这款芯片功耗2.45W,实现了0.4 LSB的微分非线性误差(DNL)和0.35 LSB的积分非线性误差(INL).低频下无杂散动态范围(SFDR)为71.53 dBc,信号频率接近奈奎斯特频率时最差的SFDR为50.54 dBc.在整个第一奈奎斯特域内,SFDR都大于50 dBc,满足高端测试仪器的应用要求.
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