The subject of this Master Thesis is the design of a 12-bit 500Ms/s standalone charge redistribution Digital-to-Analog Converter. Digital-to-Analog Converters with very high analog bandwidth are mostly built with unitary and binary weighted current sources. Their performance is limited by the matching precision of these current sources.A new type of converter based on charge redistribution can easily be operated at very high sampling rates and is built with integrated capacitors. The matching accuracy of integrated capacitors is excellent.The charge redistribution Digital-to-Analog Converter already shows fast and pretty linear settling but used as a standalone Digital-to-Analog Converter it must show a perfect ‘hold’ function and glitches between consecutive samples must be very small. In this report several possible architectures are presented that incorporate these features.Reducing the glitches and still keeping the total capacitance low are the important aspects that contributed to the choice of thermometer coding the four MSB bits and implementing the next eight bits in a binary weighted architecture with a split array.Calculations and simulations show that this architecture achieves the required matching accuracy and reduction of glitches with acceptable total capacitance. The static performance is measured and the Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) are within ±½LSB so monotonicity is guaranteed. The dynamic performance measured in the Signal-to-Noise Ratio (SNR) is close to the theoretical value of 74dB.Overall it can be concluded that the architecture presented in this report is suitable for the specified requirements; 12 bits resolution at a clock frequency of 500Ms/s with reasonable total capacitance.Future work should include further improvements in the linearity of the settling behavior, the cleaning up of the supply voltage and the design of an output buffer.
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