Design of 12-bit 500MHz CMOS current-mode DAC with deglitch circuit - design of wide bandwidth digital to analog converter

摘要

This paper describes a 12-bit 500MHz CMOS current-mode Digital to Analog Converter(DAC) consisting of 6 MSB current cell matrix stage, 2 MSB unary current source stage, and 4 LSB binary weighting stage. The linearity errors(DNL/INL) resulting from random and system errors are reduced by the proposed triple diagonally symmetrical centroid sequencing methodology. A new deglitch circuit is proposed to control a crossing point of signal and minimize a glitch energy. The simulation results show a conversion rate of 500MHz, DNL/INL of ±0.65LSB / ±0.8LSB, a glitch energy of 7.5pV.sec and a power dissipation of 84mW at 3.3V.