3D NoC网络架构设计

摘要

In the Three-dimensional Network on Chip(3D NoC) design, the pros of the communication mechanism between the layers will affect the performance of the entire 3D NoC system. In order to solve the above problem, this paper makes some improvements based on the traditional three-dimensional interconnect. For 3D NoC communication problems, this paper proposes a low hardware resource consumption, high performance bus architecture under GEMS simulation platform. It improves routing design, and bus-based 3D NoC router. Experimental results show that the architecture can increase speed-up ratio of common algorithms, and improve overall system performance.%在三维片上网络(3D NoC)设计中，层与层之间通信机制的优劣将影响整个3D NoC系统的性能。为此，在GEMS仿真平台基础上，提出一种低硬件资源消耗、高性能的总线架构，改进路由设计，构造基于总线的3D NoC的路由器。实验结果表明，该架构可提高常见算法的加速比，改善系统的整体性能。