一种基于线网划分的并行FPGA布线算法

摘要

A platform-independent multi-thread routing method for FPGA is proposed to reduce long compiling times of large design in Field Programmable Gate Array(FPGA) software system. Specifically, the proposed method includes two aspects for maximal paralleli-zation. For high fanout nets, each is partitioned into several subnets to be routed in parallel. Low fanout nets with non-overlapping boundary diagrams are identified and routed in parallel. A new graph, named boundary diagram, is constructed to facilitate the process of selecting low fanout nets to be routed concurrently. In addition, load balancing strategies and synchronization mechanisms are introduced to promote routing efficiency and ensure deterministic results. Experimental results on Intel quad-core processor platforms show that, this technique improves the average routing efficiency by 90%with routing quality degrading by no more than 2.3%and provides deterministic results, which has great theoretical and practical value in EDA field.%针对在现场可编程门阵列(FPGA)软件系统中大规模电路设计布线时间较长的问题，提出一种基于线网引脚位置划分且具有平台独立性的多线程 FPGA 布线算法。对高扇出线网采用将单根线网拆分成子线网并同时布线的方法，对低扇出线网采用选择若干位置不相交叠的线网进行同时布线的方法，给出线网边界框图的数据结构来缩短选择若干低扇出线网的时间，采取负载平衡机制和同步措施，分别提高布线效率和保证布线结果的确定性。实验结果证明，在Intel 4核处理器平台上，与单线程VPR算法相比，该并行算法的平均布线效率提高了90%，平均布线质量下降不超过2.3%，并能够得到确定的布线结果，在EDA方面具有重要的理论与实用价值。