一种高速低过冲电荷泵电路的设计

摘要

To reduce the overshoot current and improve the stability of the VCO's control voltage efficiently of conventional charge pump circuits, a new high-speed low-overshoot charge pump structure for Phase Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit has been proposed. The circuits is designed and implemented under 0.13 μm CMOS process with supply voltage of 1.2 V. The Hspice post-simulation results show that it can work well at 2.5 GHz, and compared to the conventional charge pump, the overshoot current reduced by 70%.%为了有效降低传统电荷泵电路的充放电过冲电流,提高电荷泵输出控制电压的稳定性,提出、设计并实现了一种高速低过冲的电荷泵结构,该电路适用于高速锁相环及时钟数据恢复电路.电路在电源电压为1.2 V的0.13 μm CMOS工艺下设计实现,并对版图数据进行了HSPICE模拟,其结果表明,电路在2.5 GHz的速度下能很好的工作,同时电流过冲相比传统电荷泵下降了70%.