新型全同步高分辨率DPWM设计

摘要

The advantages of digital control in power electronics,increasing the use of a digital pulse modulator (DPWM).In order to improve the DPWM's resolution and frequency,a new DPWM structure of FPGA-based embedded clock management was proposed.When the input clock frequency is constants,by using a phase shift of the clock and clock multiplier to improve DPWM's resolution and operating frequency.The experimental in Spartan-3FPGA results show that when input clock is 50 MHz,DPWM frequency is 1 MHz and resolution can reach 625 ps.%数字控制在电力电子上的优点增加了数字脉冲调制器(DPWM)的使用.为了提高DPWM分辨率和工作频率,提出一种基于FPGA内嵌时钟管理器的新型DPWM结构.在输入时钟频率不变的情况下利用时钟的相位移动和时钟倍频设计使DPWM具有更高的分辨率和工作频率.在Spartan-3 FPGA的实验结果表明当输入时钟为50 MHz,DPWM的工作频率为1 MHz,分辨率可以达到625 ps.