基于（2,1,7）卷积码实现低误码率通信的DSP设计

摘要

为降低数字通信系统传输差错并提高可靠性,从工程应用角度出发,在DSP硬件平台上实现(2,1,7)卷积码。用MATLAB仿真影响(2,1,7)卷积码性能的各个参数,与约束度为3和码率为3/4、2/3的卷积码进行对比,其仿真结果为DSP硬件实现奠定理论基础。最后选用TI公司的TMS320DM6437型号,在CCS3.3开发环境上运行。实验表明：约束度为7、码率为1/2的卷积码在较低的信噪比(SNR=6 dB)下误码率则可达到10-6,且DSP实现的(2,1,7)卷积码方便可行,快速稳定,译码准确,并具有较强的纠错能力。%In order to reduce transmission errors in digital communication systems,and enhance the reliability of the channel,from the perspective of engineering application,DSP technology is utilized to achieve(2,1,7)convolutional code. Using MATLAB to simulate the factor of affecting(2,1,7) convolutional code performance and compare that with convolutional code of constraint length 3 and code rate 3/4,2/3 respectively,the result lays the theoretical foundation for hardware implementation. Finally,TI Company's TMS320DM6437 is applied to run in CCS3. 3 envi-ronment. The experiment shows that after convolutional code of constraint length 7 and code rate 1/2,error code rate can still achieve 10-6 in lower SNR( SNR=6 dB) . And DSP hardware implements works easily,operates stably and fast,decodes correctly and has a strong error correction capability.