首页> 外国专利> DESIGN FOR LIFTED LDPC CODES HAVING HIGH PARALLELISM, LOW ERROR FLOOR, AND SIMPLE ENCODING PRINCIPLE

DESIGN FOR LIFTED LDPC CODES HAVING HIGH PARALLELISM, LOW ERROR FLOOR, AND SIMPLE ENCODING PRINCIPLE

机译:具有高并行度,低误码率和简单编码原理的高密度LDPC码设计

摘要

A method of data encoding is disclosed. An encoder receives a set of information bits and performs an LDPC encoding operation on the set of information bits to produce a codeword based on a matched lifted LDPC code. The matched lifted LDPC code is based on a commutative lifting group and includes a number of parity bits and a submatrix to determine values of the parity bits. An order of the lifting group (Z) corresponds with a size of the lifting. A determinant of the submatrix is a polynomial of the form: ga+(g0+gL)P, where g0 is the identity element of the group, g0=gL2k, and P is an arbitrary non-zero element of a binary group ring associated to the lifting group.
机译:公开了一种数据编码方法。编码器接收一组信息比特,并且对该组信息比特执行LDPC编码操作,以基于匹配的提升后的LDPC码产生码字。匹配的提升的LDPC码基于交换提升组,并且包括多个奇偶校验位和确定该奇偶校验位的值的子矩阵。提升组(Z)的顺序与提升的大小相对应。子矩阵的行列式是形式为ga +(g0 + gL)P的多项式,其中g0是组的标识元素,g0 = gL2k,P是与之相关的二元组环的任意非零元素起重小组。

著录项

  • 公开/公告号EP2957038A1

    专利类型

  • 公开/公告日2015-12-23

    原文格式PDF

  • 申请/专利权人 QUALCOMM INCORPORATED;

    申请/专利号EP20140708175

  • 发明设计人 RICHARDSON THOMAS J.;

    申请日2014-02-13

  • 分类号H03M13/11;H03M13;

  • 国家 EP

  • 入库时间 2022-08-21 14:48:29

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