基于0.11μm CMOS工艺的时域SAR模数转换器

摘要

In order to avoid the linear degradation caused by multiple delay lines,an approximation register analog-to-digital converter based on the time domain comparator is proposed. By using a single delay line to implement the time domain comparator of the mode converter,the delay line includes the numerical control delay line and the volt⁃age controlled delay line. The proposed analog-to-digital converter has 8 effective bits,with the use of an area of 0.11μm CMOS process to achieve 0.128 mm2. Experimental results show that the power consumption of the time do⁃main SAR ADC is 1.8 μW when the power supply voltage is 0.6 V.%为避免因多种延迟线之间不匹配造成的线性退化，提出了一种基于时域比较器的逐次逼近型SAR（Successive Approximation Register）模数转换器。通过使用单个延迟线来实现该模转换器的时域比较器，此延迟线包括数控延迟线和压控延迟线。提出的模数转换器具有8个有效位，使用面积为0.128 mm2的0.11μm CMOS工艺实现。实验结果表明，当工作电源电压低至0.6 V时，提出的时域SAR模数转换器功耗为1.8μW。