高精度DDS数字IP核的设计

摘要

A high precision DDS ( Direct Digital Synthesizer ) is designed to satisfy the radar system which used loop-tap,complex multiplier,linear fitting to increase the SFDR( Spurious Free Dynamic Range) . When the phase adder is 24 bit width,the used capacity of ROM is less than 1 kbyte. The simulation results show that the SFDR is greater than 110 dB,and the phase truncation is about 2 bit. So the used capacity of ROM is greatly reduced and the bit of phase truncation is also reduced, the requirement of design is achieved. After design compile using TSMC 55 nm technology,the speed can achieve 600 MHz,it also satisfies the demand of radar system.%为了满足雷达系统对高精度DDS(直接数字式频率合成器)的需求,综合使用查表法、复数旋转和线性拟合3种方法,提高DDS输出信号的无杂散动态范围SFDR.当相位累加器为24bit时,使用小于1 kbyte的ROM.仿真表明所设计的DDS,输出信号的SFDR大于110 dB,等效相位截断约为2 bit.在大幅降低对ROM使用量的同时,有效降低了相位截断的bit数,同时达到了设计要求.采用TSMC 55 nm工艺进行综合后,综合结果表明运行速度高达600 MHz,满足了雷达系统对速度的需求.