Present 3D vertical stacking technology is not thermal-scalable and is unable to stack enough layers to maximize chip performance owing to intolerable hotness. This paper proposes a novel thermal-scalable 3D parallel-heat-sinking (PHS) stacking methodology which stacks all layers parallel to the heat-sinking path. All layers are the same strip shape of short dimension parallel to and long dimension vertical to the heat-sinking path. Therefore instead of thermal throughsilicon-via (TSV), each regular silicon substrate provides an independent shorter and perfect heat-conduction path for its attached device layer because of silicon's good heat conductance. As a result, the peak substrate temperature of 3D PHS stacking chips does not increase as they stack many more layers. This paper further proposes an analytical model to compute the peak substrate temperature of 3D PHS stacking chips and to show the thermal-scalability of the methodology.Experiments on 3D integration for the future on-chip thousand-core parallel computing draw the conclusion that the 3D PHS methodology is of advantages including thermal scalability, thermalTSV free, and high yield high yield.%现有的三维(3D)垂直集成技术无法实现热扩展,受限于过高的温度,难以通过众多器件层的叠放来实现性能的最大化.文中提出了一种具有热扩展性的3D并行散热集成方法,将每个器件层平行于散热方向进行叠放,器件层为长条形,其短边平行于散热方向,长边垂直于散热方向,这样就保证了每个器件层均可以凭借自身所拥有的高导热性硅衬底(而不是导热过孔)来获得独立而较短的散热通道,保证3D并行散热集成芯片最高温度与所叠加的器件层数无关.文中提出了一种用于3D并行散热集成芯片最高衬底温度计算的分析模型,推导出3D芯片最高衬底温度的解析表达式,从理论上说明了该方法具有热扩展性.通过对未来用于千核并行计算的芯片进行3D集成设计表明:该文3D并行散热集成方法具有热扩展性、不需要导热过孔、良品率高等优点.
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