针对传统的复接器( MUX)因没有集成时钟电路而限制了其集成度及应用的问题研究了复接器与时钟电路的集成,并采用中芯国际(SMIC)0.18μm互补金属氧化物半导体(CMOS)工艺设计并实现了一个片内集成时钟产生功能的10Gb/s半速率2∶1 MUX电路.整个电路由5 Gb/s时钟提取电路(CEC)和10Gb/s半速率2∶1 MUX电路构成.CEC从一路输入数据中提取出5GHz时钟提供给MUX电路.CEC由鉴频鉴相器(PFD)、电压/电流转换电路、环路滤波器及压控振荡器(VCO)构成.Pottb(a)cker型PFD不但可以大幅度扩展环路的捕获带宽,并且由于它能够容忍高达±45°的正交相位误差,因而三级环形VCO能够被采用.测试结果表明,该电路无需任何参考时钟、外接元件及外部手动调谐即可工作.整个芯片面积为670μm ×760μm,在1.8V电压下,功耗为180mW,其中核心功耗占60％.%Considering that, conventionally, a clock function block is not integrated with a multiplexer ( MUX) , which brings restrictions to MUX' s integration and application, the research on integrating the clock circuit with a multiplexer was performed, and a 10-Gb/s half-rate 2 : 1 MUX with the integrated clock generation circuit was designed and fabricated in the SMIC 0. 18μm CMOS process. The whole circuit consists of a 5Gb/s clock extraction circuit (CEC) and a 10Gb/s half-rate 2 :1 MUX. The CEC extracts a 5GHz clock from one of two input data, and then provides the MUX with it. The CEC comprises a phase/frequency detector ( PFD) , a voltage/current converter ( V/I) , a loop filter ( LF) , and a voltage controlled oscillator ( VCO). A Pottbacker PFD can not only enlarge the pull-in range of the loop, but also tolerate up to ±45° phase error deviating from ideal inphase/quadrature (I/Q) clocks, so a 3-stage ring VCO can be employed. The measuremental results show that the circuit can work without any external component, reference clock, or manual tuning. The chip area is 670μm ×760μm. Under a 1. 8V supply, it has the power consumption of 180mW, in which, only 60% is used by the core blocks.
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