一种高线性调整率无电容型LDO的设计

摘要

提出了一种1.8V、70 mA片上集成的低功耗无电容型LDO (Low Dropout)电路.电路中采用了一级增益自举运放作为误差放大器,通过消除零点的密勒补偿技术提高了环路稳定性；带隙基准源(BGR)采用了线性化VBE技术进行高阶补偿,可以获得温度稳定性更好的BGR,降低了BGR对线性调整率的影响.该设计采用HHNEC 0.13 μm CMOS工艺(其中VTHN≈0.78 V、VTHp≈-0.9 V),整个芯片面积为0.33 mm×O.34 mm.测试结果显示:在2.5 V～5.5 V电源供电下,LDO输出的线性调整率小于2.14 mV/V,负载调整率小于1.56 mV/mA；在正常工作模式下,整个LDO消耗56 μA静态电流(其中测试用的放大器消耗电流约18 μA).%A 1.8 V and 70 mA full integrated low power capacitor-free LDO voltage regulator is presented in this paper. A folded cascode adopted gain -boosting technique amplifier is employed as the error amplifier, which using miller compensation scheme to split the nearby poles so as to improve the circuit loop stability. High-order compensation through VBE linearization supply a stable BGR under temperature variation, this can reduce the impact on line-regulation of LDO. The chip is fabricated in HHNEC 0.13 μ.m CMOS technology (with VTHN≈0.78 V and VTHP≈-0.9 V) and occupies an active area 0.33 mm×0.34 mm. The measured results demonstrate that the line regulation and load regulation are less than 2.14 mV/V and 1.56 mV/mA respectively, under the power supply ranged from 2.5 V to 5.5 V. The total LDO circuit consumes 56 μA quiescent current (including an integrated reference voltage buffer which consuming 18 μA quiescent current only for chip performance test).