一种增益自举运算放大器的分析与优化设计

摘要

In switched-capacitor circuits, settling time and accuracy are critical issues for CMOS amplifiers. In gain-boosted cascade amplifiers (CBCA), the gain bandwidth product and phase margin of main and boosting amplifiers need to be optimized for the minimum settling time. In order to simplify the optimum criteria and achieve better performance, we choose the cascade structure for boosting amplifiers with the same transfer function. Based on the analysis and optimization of this GBCA structure, we present a low-power consumption and fast-settling time CMOS amplifier design.%基于开关电容的流水线ADC设计中,运算放大器的建立时间和精度是关键指标.而增益自举运算放大器的建立时间分析比较复杂.本文通过理论推导和模型简化的方法分析其主运放和辅助运放的单位增益带宽及相位裕度对建立时间的影响.提出了一种P型与N型传输函数相同的辅助运放电路,并以此设计了一个高速、低功耗的自举运算放大器.