Techniques to Secure HW/SW-programmable SoC Architectures for Edge Computing =Sicherheitstechniken für die Datenverarbeitung an der Edge Auf HW/SW-Programmierbaren Soc-Architekturen

摘要

In order to avoid network congestion, a clear trend towards processing and analyzing an increasing amount of data at the edge of the network can be observed. Consequently, compute- and thus resource-intensive processing tasks move closer to the data source, e.g., near to the sensors. At the same time, however, the sheer number of sensors producing a huge amount of data that has to be processed in real-time raises the question of suitable compute architectures. As a result, dedicated edge platforms capable of performing such data-intensive and time-critical tasks at the edge of the network are gaining more and more interest and visibility. This work adheres to this trend yet advocates Field Programmable Gate Array (FPGA)-based System-on-Chips (SoCs), and thus both hardware- and software-programmable architectures, as ideal compute platforms to acquire and process large amounts of data right at the edge.However, when it comes to protecting edge computing and sensitive data from potential attacks against such platforms, security must play an important role. Particularly as FPGA-based edge platforms open up attack vectors not found on traditional computing devices, due to the tight integration of programmable hardware and software components. For example, an attacker with physical access to non-volatile memory could manipulate the loading of an initial FPGA configuration, which could negatively affect the entire system. Moreover, permanent SoC memory is at risk of being attacked to obtain, e.g., cryptographic keys. Such undermining of the integrity respective confidentiality of the keys poses the most significant risk, as often the security of the entire system is based on these keys. To protect FPGA devices from the threat of key-theft and manipulation, so-called Physical Unclonable Functions (PUFs) have evolved as a promising solution for permanent key storage by converting natural transistor variations into unique, FPGA-intrinsic secrets.This thesis investigates techniques to secure FPGA-based SoC devices at the edge against different security threats. As a first contribution, a novel digitally-tunable PUF design is presented that provides an alternative to insecure permanent key storage in an untrusted environment. Thereby, addressable shift registers available within the FPGA are used for the first time to generate PUF responses by adjustable signal propagation delays. It is demonstrated that these free-configurable propagation delays can be used to adjust a given PUF circuit to achieve better uniqueness and reliability propertieswithout sacrificing the PUF's unpredictability and unclonability characteristics. To this end, completely novel analyses and evaluations of the effects of temperature variation and stability are performed to investigate the impact of extreme temperatures on the robustness of the PUF. As a result, the proposed approach achieves significantly better results in uniqueness, reliability, and robustness than existing static PUF designs for FPGAs. Moreover, it is shown that this enables device-specific PUF configurations, which results in savings in error correction times and memory resources for cryptographic key generation.As a second contribution, the PUF-based key generation scheme is extended to an innovative approach for secure data communication with non-volatile memory devices. Here, the reconfigurable logic of the FPGA serves as a hardware-based root of trust for security-critical authentication and integrity checking of data transfers between SoC and memory. At power-on, a hardware-protected security unit called Trusted MemoryInterface Unit (TMIU) with access to the non-volatile memory is loaded into the FPGA. Subsequently, after appropriate authentication of the memory device, the simultaneous decryption and verification of configuration data are performed, making it possible to securely boot the entire SoC. Thus, the TMIU enables for the first time to securely handle at scale FPGA-based SoC con