A low complexity digital phase-locked loop based frequency synthesizer.

摘要

This dissertation presents a proposed low-complexity digital PLL and a digitally-controlled oscillator with an enhanced frequency resolution for frequency synthesis applications. The basic operation of the conventional PLL-based frequency synthesizers is first briefly reviewed, followed by the literature review of some reported digital PLLs. A low-complexity digital PLL is thus proposed, including the system architecture and implementations of its sub-blocks. In the proposed digital PLL, the complex digital loop filter used in many reported digital PLLs is replaced by a simple logical decision circuit, and digital encoders are avoided to significantly reduce the hardware complexity. A novel digital tuning scheme for the digitally-controlled oscillator is proposed to achieve small frequency tuning steps and to improve the matching accuracy between LSB/MSB tuning banks so that the overlaps between LSB/MSB banks can be eliminated.; The loop behavior of the proposed DPLL is analyzed theoretically and its unique noise behavior, automatic adaptation to different reference phase noise levels, is investigated, together with the determination of the design parameters. To confirm the theoretical analysis, behavioral simulations using SimuLink and the event-driven technique were done to observe the locking process and obtain the phase noise performance.; To further prove the feasibility of proposed digital PLL two test chips, the proposed high-resolution digitally controlled oscillator and the low-complexity digital PLL were implemented and fabricated. The phase noise performance and the frequency tuning characteristic of the digitally controlled oscillator were measured. The phase noise tracking and compensation characteristics were observed from the digital PLL measurements, which well agree with both the theoretical analysis and the behavioral simulations.