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Design and implementation of low power phase locked loop circuits for wireless applications.

机译:用于无线应用的低功耗锁相环电路的设计和实现。

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摘要

The wireless market has experienced an exponential growth over the past decade. To sustain this growth and increasing demands of new wireless standards, the cost, battery lifetime, and performance of wireless devices must all be enhanced. One of the most critical components in a wireless transceiver is the frequency synthesizer. With the advancement of radio frequency (RF) technology and requirement of low power, new RF architectures are needed. A phase locked loop is a typical example of a frequency synthesizer. In this thesis simple low power phase locked loops are designed and implemented for analog and digital systems.;The power consumption is a critical factor in many wireless devices. In this research, the objectives are to reduce the number of switching activity in a design and to operate the devices in the subthreshold region to reduce power consumption of the circuit.;This research analyses the phase locked loop (PLL) design for different nanoscale CMOS subsystems. The power consumption in these CMOS subsystems are evaluated for different CMOS transistor technology nodes. A single balanced topology mixer is implemented as a frequency divider circuit in the analog PLL design. A digital low power PLL consisting of full adder circuit is also designed and tested with different full adder circuits for low power consumption. Analysis of all the PLL designs and its individual components for power consumption gives us insight in choosing the simplest low power circuit.;Throughout this work, low-power has been achieved by both architectural as well as circuit techniques. All the PLL designs are simulated and tested for their proper functionality and finally they are implemented on-chip for AMI 0.5mum technology. This research work gives a detailed analysis of the PLL design and implementation, by considering most of the factors such as low cost, low power, high performance and high frequency for RF wireless applications.
机译:在过去的十年中,无线市场经历了指数级增长。为了维持这种增长和对新无线标准的不断增长的需求,必须提高无线设备的成本,电池寿命和性能。频率合成器是无线收发器中最关键的组件之一。随着射频(RF)技术的发展和对低功率的需求,需要新的RF体系结构。锁相环是频率合成器的典型示例。本文针对模拟和数字系统设计并实现了简单的低功耗锁相环。功耗是许多无线设备中的关键因素。这项研究的目的是减少设计中的开关活动数量,并在亚阈值区域内操作器件以降低电路功耗。该研究分析了针对不同纳米级CMOS的锁相环(PLL)设计子系统。针对不同的CMOS晶体管技术节点,评估了这些CMOS子系统中的功耗。在模拟PLL设计中,单个平衡拓扑混频器被实现为分频器电路。还设计并测试了由全加法器电路组成的数字低功耗PLL,并通过不同的全加法器电路进行了测试,以降低功耗。对所有PLL设计及其各个组件的功耗进行分析,使我们能够洞悉选择最简单的低功耗电路。在整个工作中,无论是架构还是电路技术都实现了低功耗。对所有PLL设计进行了仿真和测试,以了解它们的正常功能,最后它们在AMI 0.5mum技术的片上实现。这项研究工作考虑了射频无线应用的低成本,低功耗,高性能和高频率等大多数因素,从而对PLL设计和实现进行了详细分析。

著录项

  • 作者

    Nagaraju, Tilak.;

  • 作者单位

    The University of Texas at San Antonio.;

  • 授予单位 The University of Texas at San Antonio.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.S.
  • 年度 2008
  • 页码 83 p.
  • 总页数 83
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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