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Halogen-based plasma etching of novel field-effect transistor gate materials.

机译:新型场效应晶体管栅极材料的基于卤素的等离子体蚀刻。

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摘要

Vacuum Beam Studies of Ruthenium Etching. Ru is known to have two volatile oxidation products, RuO3 and RuO4, although the etch rate is negligible when Ru is exposed to an O2 plasma discharge. The introduction of a small amount of additive gas, such as Cl2, has been shown to increase the Ru etch rate sixfold. The reason for this dramatic shift in etching is poorly understood, primarily because it is difficult if not impossible to study plasma-surface interactions in a plasma environment. The unique capabilities of the beam system have made it possible to explore the mechanism of Ru etching. It has been shown that under 500 eV Ar+ ion bombardment, the addition of O radicals lowered the etch rate by a factor of 2.5. This process was relatively insensitive to temperature over the range studied (room temperature to ∼175°C). It was also shown that O radicals alone spontaneously etched Ru at a very slow rate over the entire temperature range.;Statistical Analysis of Polysilicon Etching and Gate Profile Evolution in Dual-Doped Polysilicon Gates. Polysilicon gate etching for the 90nm lithography node and below requires extremely precise control of the gate CD and profile. Generally speaking, the current requirement for Gate CD control is that the 3 sigma should less than ∼5nm for all gates, including across the chip, across the wafer, wafer-to-wafer, lot-to-lot, and tool-to-tool variations. Similarly, for gate sidewall angle control, the 3 sigma angle variation should be less than ∼1 degree, inclusive of all sources of variation. This is particularly challenging for technologies which employ dual-doped gates, since the chemistry and physics of the etching process induces a different profile evolution between gates with different doping.;The goal of this project was to identify a parameter space where the differences in gate profile evolution across different polysilicon dopant types were minimized. Blanket etch rates and patterned wafers were used to determine the effect of different gate etch process variables on the gate profile. The materials studied were undoped polysilicon and polysilicon that had been doped with P, As, Sb, and B. Prediction models were created for the blanket etch rate studies that were used to optimize the processing conditions and to propose some simple mechanisms that identify which species are adsorbed on the surface.
机译:钌蚀刻的真空束研究。已知Ru具有两种挥发性氧化产物RuO3和RuO4,尽管当Ru暴露于O2等离子体放电时蚀刻速率可以忽略不计。已经表明,引入少量的添加剂气体(例如Cl2)可以将Ru蚀刻速率提高六倍。人们对蚀刻急剧变化的原因了解甚少,主要是因为很难(即使不是不可能)研究等离子体环境中的等离子体表面相互作用。光束系统的独特功能使其有可能探索Ru蚀刻的机理。结果表明,在500 eV Ar +离子轰击下,O自由基的加入使蚀刻速率降低了2.5倍。该过程对所研究范围内的温度(室温至约175°C)相对不敏感。还表明,在整个温度范围内,O原子单独自发地以非常慢的速率自腐蚀Ru。;双掺杂多晶硅栅极中的多晶硅蚀刻和栅极轮廓演变的统计分析。用于90nm及以下工艺的多晶硅栅极蚀刻需要对栅极CD和轮廓进行极其精确的控制。一般而言,目前栅极CD控制的要求是所有栅极的3 sigma应小于〜5nm,包括整个芯片,整个晶圆,晶圆对晶圆,批对批以及工具对晶圆。工具变化。类似地,对于栅极侧壁角度控制,包括所有变化源在内,3 sigma角度变化应小于1度。对于采用双掺杂栅极的技术而言,这尤其具有挑战性,因为蚀刻工艺的化学和物理原理会在具有不同掺杂的栅极之间引起不同的轮廓演变。;该项目的目的是确定一个参数空间,其中栅极差异最小化了不同多晶硅掺杂剂类型之间的轮廓演变。毯子蚀刻速率和图案化的晶圆用于确定不同的栅极蚀刻工艺变量对栅极轮廓的影响。研究的材料是未掺杂的多晶硅和掺有P,As,Sb和B的多晶硅。创建了用于毯式蚀刻速率研究的预测模型,该模型用于优化工艺条件并提出一些简单的机制来识别哪种物种被吸附在表面上。

著录项

  • 作者

    Kiehlbaugh, Kasi Michelle.;

  • 作者单位

    University of California, Berkeley.;

  • 授予单位 University of California, Berkeley.;
  • 学科 Engineering Chemical.;Physics Fluid and Plasma.;Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 209 p.
  • 总页数 209
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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